View MSM51V17805F-70TS-K_3362256.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

oki semiconductor fedd51v17805f-02 issue date: aug. 16, 2002 msm51v17805f 2,097,152-word 8-bit dynamic ram : fast page mode type with edo 1/17 description the msm51v17805f is a 2,097,152-word 8-bit dynamic ram fabricated in oki?s silicon-gate cmos technology. the msm51v17805f achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm51v17805f is available in a 28-pin plastic tsop. features 2,097,152-word 8-bit configuration single 3.3v power supply, 0.3v tolerance input : lvttl compatible, low input capacitance output : lvttl compatible, 3-state refresh : 2048 cycles/32ms fast page mode with edo, read modify write capability cas before ras refresh, hidden refresh, ras -only refresh capability packages 28-pin 400mil plastic tsop ( tsopii28-p-400-1.27-k ) (product : msm51v17805f-xxts-k) xx indicates speed rank. product family access time (max.) power dissipation family t rac t aa t cac t oea cycle time (min.) operating (max.) standby (max.) 50ns 25ns 13ns 13ns 84ns 360mw 60ns 30ns 15ns 15ns 104ns 324mw msm51v17805f 70ns 35ns 20ns 20ns 124ns 288mw 1.8mw
fedd51v17805f-02 1 semiconductor msm51v17805f 2/17 pin configuration (top view) pin name function a0?a9, a10r address input ras row address strobe cas column address strobe dq1?dq8 data input/data output oe output enable we write enable v cc power supply (3.3v) v ss ground (0v) nc no connection note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 1 2 3 4 5 6 7 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 27 dq1 dq2 v cc v cc v ss v ss dq6 a8 a7 a6 a10r a1 a2 a3 we ras nc dq3 a5 a4 oe dq8 dq7 cas 8 dq4 20 a9 14 a0 dq5 28 28-pin plastic tsop ( k t yp e )
fedd51v17805f-02 1 semiconductor msm51v17805f 3/17 block diagram a0 ? a9 8 8 8 10 11 10 timing generator column address buffers internal address counter row address buffers refresh control clock column decoders sense amplifiers memory cells word drivers row deco- ders i/o selector input buffers output buffers dq1 ? dq 8 oe we ras cas v cc v ss on chip v bb generator i/o controller on chip iv cc generator 8 8 8 10 a10r 1
fedd51v17805f-02 1 semiconductor msm51v17805f 4/17 electrical characteristics absolute maximum ratings parameter symbol value unit voltage v cc supply relative to v ss v t ?0.5 to 4.6 v short circuit output current i os 50 ma power dissipation p d* 1 w operating temperature t opr 0 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 c recommended operating conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 0 0 0 v input high voltage v ih 2.0 ? v cc + 0.3 *1 v input low voltage v il ? 0.3 *2 ? 0.8 v notes: *1. the input voltage is v cc + 1.0v when the pulse width is less than 20ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss ? 1.0v when the pulse width is less than 20ns (the pulse width respect to the point at which v ss is applied). pin capacitance (vcc = 3.3v 0.3v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 ? a9, a10r) c in1 ? 5 pf input capacitance ( ras , cas , we , oe ) c in2 ? 7 pf output capacitance (dq1 ? dq8) c i/o ? 7 pf
fedd51v17805f-02 1 semiconductor msm51v17805f 5/17 dc characteristics (v cc = 3.3v 0.3v, ta = 0 to 70c) msm51v17805 f-50 msm51v17805 f-60 msm51v17805 f-70 parameter symbol condition min. max. min. max. min. max. unit note output high voltage v oh i oh = ? 2.0ma 2.4 v cc 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 2.0ma 0 0.4 0 0.4 0 0.4 v input leakage current i li 0v v i v cc +0.3v; all other pins not under test = 0v ? 10 10 ? 10 10 ? 10 10 a output leakage current i lo dq disable 0v v o v cc ? 10 10 ? 10 10 ? 10 10 a average power supply current (operating) i cc1 ras , cas cycling, t rc = min. ? 100 ? 90 ? 80 ma 1,2 ras , cas = v ih ? 2 ? 2 ? 2 power supply current (standby) i cc2 ras , cas v cc ? 0.2v ? 0.5 ? 0.5 ? 0.5 ma 1 average power supply current ( ras -only refresh) i cc3 ras cycling, cas = v ih , t rc = min. ? 100 ? 90 ? 80 ma 1,2 power supply current (standby) i cc5 ras = v ih , cas = v il , dq = enable ? 5 ? 5 ? 5 ma 1 average power supply current ( cas before ras refresh) i cc6 ras = cycling, cas before ras ? 100 ? 90 ? 80 ma 1,2 average power supply current (fast page mode) i cc7 ras = v il , cas cycling, t hpc = min. ? 100 ? 90 ? 80 ma 1,3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
fedd51v17805f-02 1 semiconductor msm51v17805f 6/17 ac characteristics (1/3) (v cc = 3.3v 0.3v, ta = 0 to 70c) note1,2,3 msm51v17805 f-50 msm51v17805 f-60 msm51v17805 f-70 parameter symbol min. max. min. max. min. max. unit note random read or write cycle time t rc 84 ? 104 ? 124 ? ns read modify write cycle time t rwc 110 ? 135 ? 160 ? ns fast page mode cycle time t hpc 20 ? 25 ? 30 ? ns fast page mode read modify write cycle time t hprwc 58 ? 68 ? 78 ? ns access time from ras t rac ? 50 ? 60 ? 70 ns 4, 5, 6 access time from cas t cac ? 13 ? 15 ? 20 ns 4,5 access time from column address t aa ? 25 ? 30 ? 35 ns 4,6 access time from cas precharge t cpa ? 30 ? 35 ? 40 ns 4 access time from oe t oea ? 13 ? 15 ? 20 ns 4 output low impedance time from cas t clz 0 ? 0 ? 0 ? ns 4 data output hold after cas low t doh 5 ? 5 ? 5 ? ns cas to data output buffer turn- off delay time t cez 0 13 0 15 0 20 ns 7,8 ras to data output buffer turn- off delay time t rez 0 13 0 15 0 20 ns 7,8 oe to data output buffer turn-off delay time t oez 0 13 0 15 0 20 ns 7 we to data output buffer turn- off delay time t wez 0 13 0 15 0 20 ns 7 transition time t t 1 50 1 50 1 50 ns 3 refresh period t ref ? 32 ? 32 ? 32 ms ras precharge time t rp 30 ? 40 ? 50 ? ns ras pulse width t ras 50 10,000 60 10,000 70 10,000 ns ras pulse width (fast page mode with edo) t rasp 50 100,000 60 100,000 70 100,000 ns ras hold time t rsh 7 ? 10 ? 13 ? ns ras hold time referenced to oe t roh 7 ? 10 ? 13 ? ns cas precharge time (fast page mode with edo) t cp 7 ? 10 ? 10 ? ns cas pulse width t cas 7 10,000 10 10,000 13 10,000 ns cas hold time t csh 35 ? 40 ? 45 ? ns
fedd51v17805f-02 1 semiconductor msm51v17805f 7/17 ac characteristics (2/3) (v cc = 3.3v 0.3v, ta = 0 to 70c) note1,2,3 msm51v17805 f-50 msm51v17805 f-60 msm51v17805 f-70 parameter symbol min. max. min. max. min. max. unit note cas to ras precharge time t crp 5 ? 5 ? 5 ? ns ras hold time from cas precharge t rhcp 30 ? 35 ? 40 ? ns oe hold time from cas (dq disable) t cho 5 ? 5 ? 5 ? ns ras to cas delay time t rcd 11 37 14 45 14 50 ns 5 ras to column address delay time t rad 9 25 12 30 12 35 ns 6 row address set-up time t asr 0 ? 0 ? 0 ? ns row address hold time t rah 7 ? 10 ? 10 ? ns column address set-up time t asc 0 ? 0 ? 0 ? ns column address hold time t cah 7 ? 10 ? 13 ? ns column address to ras lead time t ral 25 ? 30 ? 35 ? ns read command set-up time t rcs 0 ? 0 ? 0 ? ns read command hold time t rch 0 ? 0 ? 0 ? ns 9 read command hold time referenced to ras t rrh 0 ? 0 ? 0 ? ns 9 write command set-up time t wcs 0 ? 0 ? 0 ? ns 10 write command hold time t wch 7 ? 10 ? 13 ? ns write command pulse width t wp 7 ? 10 ? 10 ? ns we pulse width (dq disable) t wpe 7 ? 10 ? 10 ? ns oe command hold time t oeh 7 ? 10 ? 13 ? ns oe precharge time t oep 7 ? 10 ? 10 ? ns oe command hold time t och 7 ? 10 ? 10 ? ns write command to ras lead time t rwl 7 ? 10 ? 13 ? ns write command to cas lead time t cwl 7 ? 10 ? 13 ? ns data-in set-up time t ds 0 ? 0 ? 0 ? ns 11 data-in hold time t dh 7 ? 10 ? 13 ? ns 11 oe to data-in delay time t oed 13 ? 15 ? 20 ? ns cas to we delay time t cwd 30 ? 34 ? 44 ? ns 10 column address to we delay time t awd 42 ? 49 ? 59 ? ns 10 ras to we delay time t rwd 67 ? 79 ? 94 ? ns 10 cas precharge we delay time t cpwd 47 ? 54 ? 64 ? ns 10
fedd51v17805f-02 1 semiconductor msm51v17805f 8/17 ac characteristics (3/3) (v cc = 3.3v 0.3v, ta = 0 to 70c) note1,2,3 msm51v17805 f-50 msm51v17805 f-60 msm51v17805 f-70 parameter symbol min. max. min. max. min. max. unit note cas active delay time from ras precharge t rpc 5 ? 5 ? 5 ? ns ras to cas set-up time ( cas before ras ) t csr 5 ? 5 ? 5 ? ns ras to cas hold time ( cas before ras ) t chr 10 ? 10 ? 10 ? ns we to cas hold time ( cas before ras ) t wrp 10 ? 10 ? 10 ? ns we hold time from ras ( cas before ras ) t wrh 10 ? 10 ? 10 ? ns ras to we set-up time t wts 10 ? 10 ? 10 ? ns ras to we hold time t wth 10 ? 10 ? 10 ? ns
fedd51v17805f-02 1 semiconductor msm51v17805f 9/17 notes: 1. a start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 2ns. 3. v ih (min.) and v il (max.) are reference levels for measur ing input timing signals. transition times (t t ) are measured between v ih and v il . 4. -50 is measured with a load circuit equivalent to 1 ttl load and 50pf, and -6 0/-70 is measured with a load circuit equivalent to 1 ttl load and 100pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.), and t oez (max.) define the time at which the output achieved the open circuit condition and are not refe renced to output voltage levels. 8. t cez , and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating paramete rs. they are included in the data sheet as electrical characteristics only. if t wcs t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd t cwd (min.), t rwd t rwd (min.), t awd t awd (min.) and t cpwd t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of th e data out (at access time) is indeterminate. 11. these parameters are referenced to the cas , leading edges in an earl y write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
fedd51v17805f-02 1 semiconductor msm51v17805f 10/17 timing chart read cycle write cycle (early write) t cez t clz t cac t oea t asc t rrh t rah t asr t rad t ral t crp t cah t crp t rcd t rc t ras t rp t csh t rsh t cas t rac t aa t rcs t roh t rch t rez t oez row column valid data-out o p en ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol ?h? or ?l? t ds t dh t wcs t wch t cwl t asr t rah t asc t crp t rp t rc t ras t rwl t csh t crp t rcd t rsh t cas t cah t rad t ral t wp valid data-in row column ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v ih v il ?h? or ?l? o p en
fedd51v17805f-02 1 semiconductor msm51v17805f 11/17 read modify write cycle t ds t dh t oez t clz t oed t aa t oeh t rwd t cwd t cwl t rwl t cah t asc t asr t rah t rad t crp t rcd t rsh t cas t crp t cac valid data-out row t csh column t rac t oea t rcs t awd t wp t rwc t ras t rp valid data-in ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v i/oh v i/ol ?h? or ?l?
fedd51v17805f-02 1 semiconductor msm51v17805f 12/17 fast page mode read cycle (part-1) fast page mode read cycle (part-2) t hpc t rasp t csh t rcd t aa t oep t cho t cac t oep t cac t cpa t aa t oea t aa t rac t rrh t och t cah t asc t rah t rad t rcs t asr t asc t cah t cp t cas t cas t cp t crp t clz t cah valid data-out valid * data-out valid * data-out valid data-out t oea t oea t oez t cac t asc t rp t rhcp t cas t doh t oez t rez row column column column ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol ?h? or ?l? * : same data, t hpc t cas t hpc t cez valid data-out t cac valid data-out t doh t cac valid data-out t cpa t aa t rch t rcs t oea t rac t aa t rcs t crp t asr t cah t asc t rah t rad t asc t cp t asc t cah t cp t cas t rhcp t csh t rcd t clz t cah t aa t wez t cac t cas t rp ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol t rasp t wpe row column column column ?h? or ?l? t crp
fedd51v17805f-02 1 semiconductor msm51v17805f 13/17 fast page mode write cycle (early write) fast page mode read modify write cycle t dh t ds t dh t ds t dh t ds valid data-in t wch t wcs t wcs t wch t wch t wcs t asc t cah t asc t cah t rad t asr t asc t rah t rcd t crp t cas t cas t rsh t cp t cas t rp t hpc valid data-in valid data-in t csh t cah t cp t hpc t rasp row column column column ?h? or ?l? ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v ih v il t dh t oea t aa t oed t dh t oez t oeh t cac t oed t oez t oeh t awd t awd t wp t ds t aa t ds column t cwd t rcs t cah t hprwc t cpa t cwl t cah t asc t cp t rwl t rwd t cwd t rcd t crp t rasp t oea t rcs t wp t cpwd row column t rac t cac valid data - in valid data - out t clz valid data - in valid data - out t clz t rah t asr t rad t asc ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v i/oh v i/ol ?h? or ?l?
fedd51v17805f-02 1 semiconductor msm51v17805f 14/17 ras -only refresh cycle cas before ras refresh cycle t asr t rah t crp t rpc t rp t ras t rc t cez ras v ih v il cas v ih v il v ih v il address v oh v ol dq ?h? or ?l? note: we , oe = ?h? or ?l? row o p en t wrh t wrp t wrp t cez t rpc t rp t rc t ras t chr t csr t rp t cp t rpc ras v ih v il cas v ih v il v oh v ol dq o p en note: oe , address = ?h? or ?l? we v ih v il ?h? or ?l?
fedd51v17805f-02 1 semiconductor msm51v17805f 15/17 hidden refresh read cycle hidden refresh write cycle t rez t rac t clz t oez t roh t oea t cac t rrh t aa t ral t rcs t cah t rah t asr t asc column t rad t rp t ras t rc t rp t chr t ras t rsh t rcd t crp t rc ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v oh v ol o p en row valid data-out ?h? or ?l? t cez t wrp t wrh t dh t ds t wch t wcs t rwl t ral t rad t cah t rah t asr t asc t rcd t crp t rsh t rp t chr t rp t ras t rc t rc t ras t wp ras v ih v il cas v ih v il address v ih v il we v ih v il oe v ih v il dq v ih v il row column valid data-in ?h? or ?l? t wrp t wrh
fedd51v17805f-02 1 semiconductor msm51v17805f 16/17 revision history page document no. date previous edition current edition description fedd51v17805f-01 dec, 2000 ? ? final edition 1 fedd51v17805f-02 aug, 2002 1, 2 1, 2 deleted soj package
fedd51v17805f-02 1 semiconductor msm51v17805f 17/17 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are refl ected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to , operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, ne glect, improper installati on, repair, alteration or accident, improper handling, or unusual physi cal or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s in dustrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability char acteristics nor in any system or ap plication where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tr affic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

▲Up To Search▲

Price & Availability of MSM51V17805F-70TS-K

	To Download MSM51V17805F-70TS-K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .